1. Field of the Invention
Example embodiments of the present invention relate generally to semiconductor memory devices, block select decoding circuits and a method thereof, and more particularly to semiconductor memory devices, block select decoding circuits and a method of activating a word line.
2. Description of the Related Art
A conventional semiconductor memory device may be used to store data. A number of volatile random access memory (RAM) devices in a computer. A dynamic random access memory (DRAM) may be included among the RAM devices, and may have a plurality of memory cells. A memory cell typically may include a transistor and a capacitor. The capacitor may store an electric charge to represent a first logic level (e.g., a higher logic level or logic “1”) or a second logic level (e.g., a lower logic level or logic “0”). Because the electric charge stored in the capacitor may be discharged over time, the capacitor of the memory cell may be periodically refreshed.
The memory cell of the DRAM may be electrically connected to a word line and a bit line. If the transistor of the memory cell is turned on in response to a word line enable signal, data stored in the capacitor may be outputted to the bit line or data on the bit line may be stored in the capacitor as a form of electric charge. Conventional semiconductor memory devices may have a folded bit line architecture or an open bit line architecture.
FIG. 1 is a schematic diagram illustrating a conventional semiconductor memory device with a folded bit line architecture.
Referring to FIG. 1, the semiconductor memory device (e.g., a DRAM device) may include a memory cell array 8 and sense amplifiers 2, 4 and 6. The memory cell array 8 may include a plurality of memory cells that each may include a transistor and a capacitor. Each of the memory cells may be electrically connected to a corresponding word line and a corresponding bit line. The folded bit lines in the folded bit line DRAM device in FIG. 1 may make pairs. Data D0 and D0B on the bit line pair may be amplified by the sense amplifier 2, data D1 and D1B on the bit line pair may be amplified by the sense amplifier 4 and Data D2 and D2B on the bit line pair may be amplified by the sense amplifier 6.
FIG. 2 is a schematic diagram illustrating a conventional semiconductor memory device with an open bit line architecture.
Referring to FIG. 2, the conventional semiconductor memory device (e.g., a DRAM device) may include memory cell arrays 16 and 18 and sense amplifiers 12 and 14. The memory cell array 16 and the memory cell array 18 may be symmetrically disposed respective sides of the sense amplifiers 12 and 14. Data D1 on the bit-line of the memory cell array 16 and data D1B on the bit line of the memory cell array 18, which may be symmetrically disposed to respective sides of the sense amplifier 12, may make a pair and may be complementary to each other. Data D0 on the bit line of the memory cell array 16 and data D0B on the bit line of the memory cell array 18, which may be symmetrically disposed to respective sides of the sense amplifier 14, may make a pair and may be complementary to each other.
FIG. 3 is a conceptual diagram illustrating an edge memory block of a DRAM device with an open bit line architecture.
Referring to FIG. 3, the DRAM device may include memory blocks BLOCK#0, . . . , BLOCK#(N−1), and BLOCK#N and sense amplifiers may be disposed between memory blocks BLOCK#0, . . . , BLOCK#(N−1), and BLOCK#N.
Column lines of the memory blocks BLOCK#0, . . . , BLOCK#(N−1) and BLOCK#N may correspond to word lines and row lines of the memory blocks BLOCK#0, . . . , BLOCK#(N−1) and BLOCK#N may correspond to bit lines. ‘VBL’ may denote a bit line precharge voltage. For example, the bit line precharge voltage VBL may be one half of a power voltage VDD. The open bit line DRAM device in FIG. 3 may allow a cell area of six times of F2 in which F may denote a distance between two adjacent bit lines, and thus the open bit line architecture in FIG. 3 may be referred to as 6F2 architecture.
The bits lines BL and BLB, which may make a pair, may be disposed at left and right sides, respectively, of the sense amplifier in the open bit line DRAM device of FIG. 3. However, the memory blocks BLOCK#0 and BLOCK#N, which may be disposed respectively at left and right boundaries or edges of the memory cell array, may include bit lines that do not make a pair (e.g., bit lines coupled to unpaired memory cells indicated with dark-colored circles in FIG. 3). The unpaired memory cells may not be coupled to the sense amplifier, and instead may be dummy cells that may not be configured to store data.
A bit line in the memory block BLOCK#0 may make a pair (e.g., bit lines coupled to memory cells indicated with white-colored circles in FIG. 3) with a bit line in the memory block BLOCK#1. Therefore, word lines of the edge memory block BLOCK#0 disposed at the left edge of the memory cell array and word lines of the edge memory block BLOCK#N disposed at the right edge of the memory cell array may be concurrently activated.
FIG. 4 is a schematic view illustrating a DRAM device having a plurality of memory banks.
Referring to FIG. 4, the semiconductor memory device may include four memory banks BANK A, BANK B, BANK C and BANK D. Each of the memory banks BANK A, BANK B, BANK C and BANK D may include N+1 memory blocks BLOCK#0 through BLOCK#N.
FIG. 5 is a conceptual diagram illustrating an activation of a word line within the DRAM device in FIG. 4. Hereinafter, an activation of word lines in a memory block may be, for the sake of brevity, referred to as an activation of the respective memory block itself.
In the DRAM device in FIG. 5, the memory blocks of the respective memory banks BANK A, BANK B, BANK C and BANK D may have identical or corresponding addresses, such as BLOCK#0 through BLOCK#N. The two memory blocks BLOCK#0 and BLOCK#N may be edge memory blocks and the other memory blocks (e.g., other than the edge memory blocks) may be referred to as “normal” (i.e., non-edge) memory blocks BLOCK#1 through BLOCK#N−1.
Referring to FIG. 5, the edge memory blocks BLOCK#0 and BLOCK#N, which may be disposed on both edges of the respective memory banks, may be concurrently activated (e.g., indicated with solid lines), and the normal memory blocks may be activated independently (e.g., indicated with dashed lines). In FIG. 5, the memory block BLOCK#2 may be representative of a normal memory block that may be activated.
Each of the plurality of memory banks BANK A, BANK B, BANK C and BANK D may be concurrently activated in a refresh mode. However, if word lines in the edge memory blocks of all the memory banks are concurrently activated, a higher word line enable voltage VPP may be required, which may increase power consumption as well as circuit noise in a conventional semiconductor memory device having a plurality of memory banks.
Generally, only one of the “normal” memory blocks may be activated at a given time, while two word lines in the edge memory block may be activated at a given time. Therefore, in the semiconductor memory device in FIG. 5, a ratio of a number of concurrently activated word lines with only the normal memory blocks activated (e.g., in all of the memory banks) to a number of concurrently activated word lines when edge memory blocks are activated may be 1:2.
Accordingly, if the word lines of the semiconductor memory device having a plurality of memory banks are activated, the concurrent activation of the edge memory blocks BLOCK#0 and BLOCK#N for two or more memory banks may cause an increase in a word line enable voltage VPP, thereby generating an increased amount of noise.